1. Field of the Invention
The present invention relates to a structure of a semiconductor integrated circuit device for dielectric isolation between circuits elements contained in the device, and more particularly to such a structure having grooves or trenches wherein an insulator material is embedded.
2. Description of the prior art
Heretofore, it has widely been known for dielectric isolation between circuit elements of a semiconductor integrated circuit device to locally oxidate a silicon substrate of the device. This technique is called local oxidation of silicon (LOCOS). Further, in order to accommodate the requirement of more and more minute structure in the field of semiconductor integrated circuit devices, it has been proposed to modify the LOCOS structure or to form trenches on the semiconductor substrate surface and embed a silicon oxide layer in the trenches.
Now referring to FIG. 9, a currently employed dielectric isolation structure for circuit elements is explained. This FIG. 9 shows a general structure of an N-channel metal-oxide semiconductor field-effect-transistor (MOSFET) by way of a sectional view. On a silicon substrate 91 having a p-type conductivity, a channel stopper region 92 having a p.sup.+ -type conductivity higher than the impurity concentration in the silicon substrate 91 is provided and on this region, a thick silicon oxide film is formed by a known selective thermal oxidation method using a silicon nitride film as a mask to provide a dielectric isolation film 93 for circuit elements. The channel stopper region 92 and the dielectric isolation film 93 surround the MOSFET to ensure electric isolation from adjacent MOSFETs. This MOSFET is constituted by source/drain regions 94 formed by an n.sup.+ layer, a gate insulation film 95, a gate electrode 96 and metal leads 98 as outgoing lines from the source/drain regions formed on an interposed layer-isolation film 97. This device is finally covered with a passivation film 99 for ensuring reliability.
Such a prior art element isolation structure as described above however is not suitable for extremely minute elements in, for example, a very large scale integrated circuit (VLSI). Since thermal oxidation is used to form the dielectric isolation film 93, the oxide film also grows in a lateral direction to form what are called bird's beaks and so it is impractical to effect selective oxidation of minute regions. It has therefore been proposed to form grooves on a silicon substrate surface and embed a silicon oxide film therein, but such technique has not as yet been completed as an industrially employable one.
In effect, when a width of an element isolation region becomes less than 0.5 .mu.m, formation of bird's beaks or crystal defects owing to thermal stress occurs frequently in the prior art LOCOS or modified LOCOS structure and so it is impractical to accommodate to 64M dynamic random access memory (DRAM) class VLSI.
Further, in the prior art technique of forming trenches on a silicon semiconductor substrate surface and embedding a silicon oxide film therein, there is a problem that a large stress of more than 10.sup.9 dync/cm.sup.2 is generated in the silicon substrate and crystal defects are liable to occur in the substrate when the substrate is subjected to a thermal treatment, due to the difference between the thermal expansion coefficients of the silicon oxide film and the substrate. Moreover in this technique, in a process step of hydrofluoric acid treatment which is essential for producing a semiconductor device, a part of the silicon oxide film embedded in the trenches is removed to expose upper corner portions of the trenches and therefore to form channel regions of the MOSFET also on upper inside wall of the trenches. In the channel regions as formed above, a larger amount of current is leaked and so transistor properties are impaired.